The field of this invention relates generally to protective enclosures for electronic components and, more particularly, to systems and method for protecting recorded data in a memory from post crash effects.
At least some known crash-protected memories (CPM) for flight data recorders (FDR) utilize a solid-state memory for preserving data recorded during a flight or other transit of a vehicle for analysis in the event of, for example, a crash. Such CPMs typically use Single-Level Cell (SLC) NAND Flash memory devices utilizing 50 nm or larger lithography to meet the data survivability requirements for Flight Data Recorders (FDRs). The relatively wide guard-band in the level of charge that determines a logical “1” or a “0” tolerates a certain level of degradation in the cell before it fails. However, this guard-band is reduced geometrically as lithographies are reduced in order to meet manufacturing price targets and yields. As the solid-state memory devices utilized in the crash-protected memory (CPM) modules use smaller and smaller lithographies, their ability to retain data at high temperatures begins to diminish. Exposure to high temperatures associated with a burn event of a crash incident eventually produces random bit failures that corrupt the data stored within the CPM. While the addition of Error Correcting Code (ECC) circuitry plus its additional memory devices is one potential solution to maintaining data integrity, the additional power required of the ECC circuitry must also be dissipated within the CPM and adds to the thermal management issues in the CPM. Eventually, SLC NAND Flash technology will no longer be suitable for use within a CPM.